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ASIC Implementation of High Speed Area Efficient Arithmetic Unit using GDI based Vedic Multiplier

Journal Name:

  • International Journal of Applied Research and Technology

Publication Year:

  • 2017
DOI: 
https://doi.org/10.24163/ijart/2017/2(2):146-152

Key Words:

Author Name
Abstract (2. Language): 
The Concentration of this paper is the designing and implementation of an Arithmetic Logic Unit (ALU) using certain area optimizing techniques such as Vedic Multiplier Algorithm for Multiplication Process & Gate-Diffusion-input (GDI) logic for basic elements. The main sub-blocks of ALU are Adder, Multiplier, Multiplexer and Logical Block. This paper evaluates and compares the performance and optimized area of ALU with CMOS technique and GDI technique in 180nm CMOS process technology. Simulations are performed by using Cadence 180nm technology and compared with CMOS logic realization. The simulation gives that design of ALU through GDI is more efficient with low power consumption, decreases area and faster compared with CMOS logic.
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  • 2
146
152
  • English

REFERENCES

References: 

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